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Proceedings Paper

FFT communications requirement optimizations on massively parallel architectures with local and global interprocessor communications capabilities
Author(s): Christopher L. Kuszmaul
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Paper Abstract

Fast Fourier Transforms [1] Batcher sorting [2] Cyclic Reduction [3] and a host of other recursively defined divide and conquer style algorithms can be implemented on massively parallel computers which provide for rapid communications between data elements whose indices differ by a power of two. This paper addresses the general issue of how two different communication mechanisms one Global and one Local can provide for hybrid performance that substantially exceeds what either could provide separately. In particular power of two communications schemes are explored for the MP-1 family ofmassively parallel computers. By using a combination of the eight way nearest neighbor toroidally wrapped grid and the Global Router on an MP-1 1200 series computer with 16 processors (PEs) the communications requirements for a 16 point FFT are shown to require less than 2 milliseconds.

Paper Details

Date Published: 1 November 1990
PDF: 12 pages
Proc. SPIE 1348, Advanced Signal Processing Algorithms, Architectures, and Implementations, (1 November 1990); doi: 10.1117/12.23497
Show Author Affiliations
Christopher L. Kuszmaul, Maspar Computer Corp. (United States)

Published in SPIE Proceedings Vol. 1348:
Advanced Signal Processing Algorithms, Architectures, and Implementations
Franklin T. Luk, Editor(s)

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