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Proceedings Paper

Implementation of still-image compression-decompression scheme on FPGA circuits
Author(s): Frederic Truchetet; Andre Forys
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Paper Abstract

We present in this paper a hardware implemented system which allows compression and decompression of 256 X 256 still-images at almost video rate. We have followed a scheme inspired from those presented by Barland. In the compression stage, the main steps are: biorthogonal wavelet transform (5 levels), scalar and vector quantization of the last two levels, lossless coding; the decompression stage follows the same steps in their inverse forms. We have tested the robustness of the reconstruction in the presence of truncatures made on the wavelet coefficients, and it seems that the use of wavelet with high regularity filter is not really important in the compression stage. Finally we have chosen FIR splines filters with 3 coefficients for analysis and 5 for synthesis. The wavelet coefficients are truncated and coded in a non linear way. The codebook is created once for all with a set of training images using an algorithm inspired from Chok-Ki Chan. The hardware implementation has required 4 FPGA circuits and some RAM. For a 256 X 256 image with gray levels coded on bytes the compression time is 64 ms while the decompression time is 17 ms with a compression ratio of 87 and a mean PSNR of 28 dB.

Paper Details

Date Published: 13 March 1996
PDF: 10 pages
Proc. SPIE 2669, Still-Image Compression II, (13 March 1996); doi: 10.1117/12.234756
Show Author Affiliations
Frederic Truchetet, Univ. de Bourgogne (France)
Andre Forys, Univ. de Bourgogne (France)


Published in SPIE Proceedings Vol. 2669:
Still-Image Compression II
Robert L. Stevenson; Alexander I. Drukarev; Thomas R. Gardos, Editor(s)

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