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Proceedings Paper

Image processing using simplified Kohonen network
Author(s): Hiroyuki Araki; Hikaru Fukumoto; Tadashi Ae
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Paper Abstract

We have designed a neuro-chip for Kohonen learning vector quantization (LVQ) algorithm, and fabricated it by gate-arrays, which includes 12 neurons/chip. We proposed a simplified version for Kohonen LVQ algorithm, because the gate-array restricts the number of transistors. Moreover, the fixed-point calculation is inevitable in neuro-chip. In this paper we demonstrate a good performance of our chip, which is used for bit-pattern image processing. For real-time systems learning can be done in real-time as well as i/o response. The neuro- chip can execute learning procedure (actually, Kohonen LVQ algorithm) in real-time. The first-version chip (already realized) can execute 32 bit patterns, but the second version will be enlarged to 256 bit pattern processing. The neurons become as much as chips are connected to a bus. The demonstration board using the first-version chips includes four chips, i.e., 48 neurons, which corresponds to 48 patterns recognition.

Paper Details

Date Published: 5 March 1996
PDF: 10 pages
Proc. SPIE 2661, Real-Time Imaging, (5 March 1996); doi: 10.1117/12.234653
Show Author Affiliations
Hiroyuki Araki, Hiroshima Univ. (Japan)
Hikaru Fukumoto, Hiroshima Univ. (Japan)
Tadashi Ae, Hiroshima Univ. (Japan)


Published in SPIE Proceedings Vol. 2661:
Real-Time Imaging
Phillip A. Laplante; Alexander D. Stoyenko; Divyendu Sinha, Editor(s)

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