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Proceedings Paper

Design of a high-speed optical arithmetic unit
Author(s): Susamma Barua
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Paper Abstract

The design of a high-speed, parallel arithmetic unit using the redundant binary representation is presented. The arithmetic unit consists of an adder and multiplier. The adder performs the addition/subtraction of two numbers in a single stage independent of the length of the numbers and the multiplier performs the multiplication in a computation time of O(log n) with O(n squared) computational elements.

Paper Details

Date Published: 27 December 1990
PDF: 10 pages
Proc. SPIE 1347, Optical Information Processing Systems and Architectures II, (27 December 1990); doi: 10.1117/12.23440
Show Author Affiliations
Susamma Barua, California State Univ./Fullerton (United States)


Published in SPIE Proceedings Vol. 1347:
Optical Information Processing Systems and Architectures II
Bahram Javidi, Editor(s)

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