Share Email Print

Proceedings Paper

High-level design methodology for the implementation of image processing ASICs
Author(s): Mohamed A. Wahab; Iain W. Shewring; S. John Rees
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper presents an integrated design methodology for the development of high-level image processing algorithms and their ASIC implementation. A commercially available DSP development system is utilized to implement this strategy. A 2-D DCT algorithm is used as an example to illustrate the smooth transition between high-level algorithm development and hardware synthesis.

Paper Details

Date Published: 27 February 1996
PDF: 9 pages
Proc. SPIE 2727, Visual Communications and Image Processing '96, (27 February 1996); doi: 10.1117/12.233315
Show Author Affiliations
Mohamed A. Wahab, Univ. of Glamorgan (United Kingdom)
Iain W. Shewring, Univ. of Glamorgan (United Kingdom)
S. John Rees, Univ. of Glamorgan (United Kingdom)

Published in SPIE Proceedings Vol. 2727:
Visual Communications and Image Processing '96
Rashid Ansari; Mark J. T. Smith, Editor(s)

© SPIE. Terms of Use
Back to Top