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Backscattered electron simulations to evaluate sensitivity against electron dosage of buried semiconductor features
Author(s): Maseeh Mukhtar; Bradley Thiel
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Paper Abstract

In fabrication, overlay measurements of semiconductor device patterns have conventionally been performed using optical methods. Beginning with image-based techniques using box-in-box to the more recent diffraction-based overlay (DBO). Alternatively, use of SEM overlay is under consideration for in-device overlay. Two main application spaces are measurement features from multiple mask levels on the same surface and buried features. Modern CD-SEMs are adept at measuring overlay for cases where all features are on the surface. In order to measure overlay of buried features, HV-SEM is needed. Gate-to-fin and BEOL overlay are important use cases for this technique. A JMONSEL simulation exercise was performed for these two cases using 10 nm line/space gratings of graduated increase in depth of burial. Backscattered energy loss results of these simulations were used to calculate the sensitivity measurements of buried features versus electron dosage for an array of electron beam voltages.

Paper Details

Date Published: 13 March 2018
PDF: 11 pages
Proc. SPIE 10585, Metrology, Inspection, and Process Control for Microlithography XXXII, 105852L (13 March 2018); doi: 10.1117/12.2314665
Show Author Affiliations
Maseeh Mukhtar, SUNY Polytechnic Institute (United States)
Bradley Thiel, SUNY Polytechnic Institute (United States)


Published in SPIE Proceedings Vol. 10585:
Metrology, Inspection, and Process Control for Microlithography XXXII
Vladimir A. Ukraintsev, Editor(s)

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