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Monitor and control for the SKA1 CSP Mid.CBF utilizing the Stratix-10 FPGA equipped with HPS
Author(s): David A. Del Rizzo; Mark A. B. Garstin
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Paper Abstract

We present design considerations and a prototyping progress report for a low-level monitor and control communication system designed to operate on the Stratix-10 System on a Chip (SoC) Field Programmable Gate Array (FPGA) equipped with a Hard Processor System (HPS). The goal of this activity is to allow remote clients to use high level communication protocols (ie. TANGO) to access IP blocks within a Stratix-10 FPGA chip by taking advantage of very low latency communication between HPS and the FPGA fabric, eliminating the need to implement Ethernet protocols within the FPGA logic.

Paper Details

Date Published: 6 July 2018
PDF: 8 pages
Proc. SPIE 10707, Software and Cyberinfrastructure for Astronomy V, 107071S (6 July 2018); doi: 10.1117/12.2309986
Show Author Affiliations
David A. Del Rizzo, National Research Council Canada (Canada)
Mark A. B. Garstin, National Research Council Canada (Canada)


Published in SPIE Proceedings Vol. 10707:
Software and Cyberinfrastructure for Astronomy V
Juan C. Guzman; Jorge Ibsen, Editor(s)

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