Share Email Print
cover

Proceedings Paper

A low-power CMOS readout IC with on-chip column-parallel SAR ADCs for microbolometer applications
Author(s): Atia Shafique; Ömer Ceylan; Melik Yazici; Mehmet Kaynak; Yasar Gurbuz
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

A readout IC (ROIC) designed for high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The ROIC is designed for higher Ge content SiGe microbolometers which have higher detector resistance (~1M Ω) and higher TCR values (~%5.5/K). The ROIC includes column SAR ADCs for on-chip column-parallel analog to digital conversion. SAR ADC architecture is chosen to reduce the overall power consumption. The problem of resistance variation across the bolometers which introduce fixed pattern noise is addressed by setting a tunable reference resistor shared for each column which can be calibrated offline to set the common-mode level. Moreover, column non-uniformity has been reduced through comparator offset compensation in the SAR ADC. The columnwise architecture in this work reduces the number of integrators needed in the architecture and enables 17x17 μm2 pixel sizes. The prototype has been designed and fabricated in 0.25-μm CMOS process.

Paper Details

Date Published: 25 May 2018
PDF: 7 pages
Proc. SPIE 10624, Infrared Technology and Applications XLIV, 1062422 (25 May 2018); doi: 10.1117/12.2304994
Show Author Affiliations
Atia Shafique, Sabanci Univ. (Turkey)
Ömer Ceylan, Sabanci Univ. (Turkey)
Melik Yazici, Sabanci Univ. (Turkey)
Mehmet Kaynak, Sabanci Univ. (Turkey)
Yasar Gurbuz, Sabanci Univ. (Turkey)


Published in SPIE Proceedings Vol. 10624:
Infrared Technology and Applications XLIV
Bjørn F. Andresen; Gabor F. Fulop; Charles M. Hanson; John Lester Miller; Paul R. Norton, Editor(s)

© SPIE. Terms of Use
Back to Top