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An acceleration system for Laplacian image fusion based on SoC
Author(s): Liwen Gao; Hongtu Zhao; Xiujie Qu; Tianbo Wei; Peng Du
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Paper Abstract

Based on the analysis of Laplacian image fusion algorithm, this paper proposes a partial pipelining and modular processing architecture, and a SoC based acceleration system is implemented accordingly. Full pipelining method is used for the design of each module, and modules in series form the partial pipelining with unified data formation, which is easy for management and reuse. Integrated with ARM processor, DMA and embedded bare-mental program, this system achieves 4 layers of Laplacian pyramid on the Zynq-7000 board. Experiments show that, with small resources consumption, a couple of 256×256 images can be fused within 1ms, maintaining a fine fusion effect at the same time.

Paper Details

Date Published: 10 April 2018
PDF: 8 pages
Proc. SPIE 10615, Ninth International Conference on Graphic and Image Processing (ICGIP 2017), 1061537 (10 April 2018); doi: 10.1117/12.2303486
Show Author Affiliations
Liwen Gao, Beijing Institute of Technology (China)
Hongtu Zhao, Beijing Institute of Technology (China)
Xiujie Qu, Beijing Institute of Technology (China)
Tianbo Wei, Beijing Institute of Technology (China)
Peng Du, Beijing Institute of Technology (China)


Published in SPIE Proceedings Vol. 10615:
Ninth International Conference on Graphic and Image Processing (ICGIP 2017)
Hui Yu; Junyu Dong, Editor(s)

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