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Proceedings Paper

Applying machine learning to pattern analysis for automated in-design layout optimization
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Paper Abstract

Building on previous work for cataloging unique topological patterns in an integrated circuit physical design, a new process is defined in which a risk scoring methodology is used to rank patterns based on manufacturing risk. Patterns with high risk are then mapped to functionally equivalent patterns with lower risk. The higher risk patterns are then replaced in the design with their lower risk equivalents. The pattern selection and replacement is fully automated and suitable for use for full-chip designs. Results from 14nm product designs show that the approach can identify and replace risk patterns with quantifiable positive impact on the risk score distribution after replacement.

Paper Details

Date Published: 10 April 2018
PDF: 9 pages
Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 1058805 (10 April 2018); doi: 10.1117/12.2299492
Show Author Affiliations
Jason P. Cain, Advanced Micro Devices, Inc. (United States)
Moutaz Fakhry, Advanced Micro Devices, Inc. (United States)
Piyush Pathak, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Frank Gennari, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 10588:
Design-Process-Technology Co-optimization for Manufacturability XII
Jason P. Cain, Editor(s)

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