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A compact multi-bit flip-flop with smaller height implementation and metal-less intra-cell routing
Author(s): Jaewoo Seo; Jinwook Jung; Youngsoo Shin
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Paper Abstract

Multi-bit flip-ops (MBFFs) are widely used in modern circuit designs because of their lower power consumption and smaller footprint. However, conventional MBFFs have routability issues due to the dense intra-cell connections. Since many horizontal connections are populated in the typical MBFF layouts, metal-2 (M2) tracks are highly occupied inside the cell. Accordingly, routers cannot leverage the M2 tracks for inter-cell connections. The conventional MBFFs also show a limited impact on the cell area reduction. Since the cell area saving of an MBFF mainly comes from the clock driver sharing, the layouts of other ip-op modules remain almost the same. In this paper, we propose a compact MBFF with metal-less clock routing and smaller height implementation. To achieve a sparse population of M2 routing tracks, we vertically place MBFF modules and interconnect them using the poly layer. As a result, the wire length of M2 layer inside a cell is significantly reduced. We also propose the smaller cell height implementation for compact MBFF layouts. Assuming the default standard cell height of 9 tracks, we present a 6-track MBFF implementation and the glue logic which makes legal cell placement with the 9-track logic cells. Experiments with a few test circuits show that the number of routing grids having congestion overflow is reduced by 16% and 73%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively. Total cell area is also reduced by 8% and 2%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively.

Paper Details

Date Published: 20 March 2018
PDF: 10 pages
Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880A (20 March 2018); doi: 10.1117/12.2297519
Show Author Affiliations
Jaewoo Seo, KAIST (Korea, Republic of)
SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Jinwook Jung, KAIST (Korea, Republic of)
Youngsoo Shin, KAIST (Korea, Republic of)


Published in SPIE Proceedings Vol. 10588:
Design-Process-Technology Co-optimization for Manufacturability XII
Jason P. Cain, Editor(s)

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