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Proceedings Paper

Litho friendly via insertion with in-design auto-fix flow using machine learning
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Paper Abstract

Via failure has always been a significant yield detractor caused by random and systematic defects. Introducing redundant vias or via bars into the design can alleviate the problem significantly [1] and has, therefore, become a standard DFM procedure [2]. Applying rule-based via bar insertion to convert millions of via squares to via bar rectangles, in all possible places where enough room could be predicted, is an efficient methodology to maximize the redundancy rate. However, inserting via bars can result in lithography hotspots. A Pattern Manufacturability (PATMAN) model is proposed, to maximize the Redundant Via Insertion (RVI) rate in a reasonable runtime, while insuring lithography friendly insertion based on the accumulated DFM learnings during the yield ramp.

Paper Details

Date Published: 4 April 2018
PDF: 11 pages
Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880F (4 April 2018); doi: 10.1117/12.2297499
Show Author Affiliations
Ahmed Mounir Elsemary, GLOBALFOUNDRIES Inc. (United States)
Moutaz Fakhry, Advanced Micro Devices, Inc. (United States)
Janam Bakshi, GLOBALFOUNDRIES Inc. (United States)
Nishant Shah, GLOBALFOUNDRIES Inc. (United States)
Mohamed Ismail, GLOBALFOUNDRIES Inc. (United States)
Fadi Batarseh, GLOBALFOUNDRIES Inc. (United States)
Uwe Paul Schroeder, GLOBALFOUNDRIES Inc. (United States)
Ahmed Mohyeldin, GLOBALFOUNDRIES Inc. (United States)
Jason Cain, Advanced Micro Devices, Inc. (United States)


Published in SPIE Proceedings Vol. 10588:
Design-Process-Technology Co-optimization for Manufacturability XII
Jason P. Cain, Editor(s)

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