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Proceedings Paper

Cost modeling 22nm pitch patterning approaches
Author(s): Ed Korczynski
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Paper Abstract

No single lithography technology can create <24nm pitch patterns in a single pass except for direct-write e-beam which is too slow and expensive for HVM. Various complex multi-patterning process flows can be compared by Cost Per Wafer Pass (CPWP), a term defined as the cost-of-ownership (CoO) with all yield losses set to zero in high volume manufacturing (HVM). CPWP modeling allows for the evaluation of alternate 1D and 2D patterning paths, including EUV LE2, EUV SADP, ArFi LE4, ArFi SAQP + EUV cut-mask, and ArFi SADP + DSA + ArFi block-mask. Similar CPWP for ArFi- and EUV-based flows favor the latter due to reduced yield losses and manufacturing times.

Paper Details

Date Published: 20 March 2018
PDF: 6 pages
Proc. SPIE 10589, Advanced Etch Technology for Nanopatterning VII, 105890R (20 March 2018); doi: 10.1117/12.2297454
Show Author Affiliations
Ed Korczynski, Techcet CA LLC (United States)


Published in SPIE Proceedings Vol. 10589:
Advanced Etch Technology for Nanopatterning VII
Sebastian U. Engelmann, Editor(s)

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