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Self-aligned blocking integration demonstration for critical sub-30nm pitch Mx level patterning with EUV self-aligned double patterning
Author(s): Angélique Raley; Joe Lee; Jeffrey T. Smith; Xinghua Sun; Richard A. Farrell; Jeffrey Shearer; Yongan Xu; Akiteru Ko; Andrew W. Metz; Peter Biolsi; Anton Devilliers; John Arnold; Nelson Felix
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Paper Abstract

We report a sub-30nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology (SAB) targeting the back end of line (BEOL) metal line patterning applications for logic nodes beyond 5nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193nm immersion SADP targeting a 40nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, Spin on carbon, spin on glass). The multi-color integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and more generally edge placement error (EPE) as a whole for advanced process nodes. Unbiased LER/LWR analysis comparison between EUV SADP and 193nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open and dielectric etch compared to 193nm immersion SADP, the final process performance is matched in terms of LWR (1.08nm 3 sigma unbiased) and is only 6% higher than 193nm immersion SADP for average unbiased LER. Using EUV SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged, and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.

Paper Details

Date Published: 4 April 2018
PDF: 11 pages
Proc. SPIE 10589, Advanced Etch Technology for Nanopatterning VII, 105890L (4 April 2018); doi: 10.1117/12.2297438
Show Author Affiliations
Angélique Raley, Tokyo Electron Ltd. (United States)
Joe Lee, IBM Research (United States)
Jeffrey T. Smith, Tokyo Electron Ltd. (United States)
Xinghua Sun, Tokyo Electron Ltd. (United States)
Richard A. Farrell, Tokyo Electron Ltd. (United States)
Jeffrey Shearer, IBM Research (United States)
Yongan Xu, IBM Research (United States)
Akiteru Ko, Tokyo Electron Ltd. (United States)
Andrew W. Metz, Tokyo Electron Ltd. (United States)
Peter Biolsi, Tokyo Electron Ltd. (United States)
Anton Devilliers, Tokyo Electron Ltd. (United States)
John Arnold, IBM Research (United States)
Nelson Felix, IBM Research (United States)


Published in SPIE Proceedings Vol. 10589:
Advanced Etch Technology for Nanopatterning VII
Sebastian U. Engelmann, Editor(s)

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