Share Email Print

Proceedings Paper

Design for nanoimprint lithography: hot spot modification through total NIL process simulation
Author(s): Sachiko Kobayashi; Kyoji Yamashita; Hirotaka Tsuda; Kazuhiro Washida; Motofumi Komori; Ji-Young Im; Takuya Kono; Tetsuro Nakasugi
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. Layout and process dependent hotspots become a significant issue for application in smaller pattern size device and, design for manufacturing (DFM) flow comprising imprint process has to be prepared. Focusing on resist drop arrangement method as a process margin expansion knob, simulated non-fill defect is compared with experimental result. Finally, drop arrangement-related hot-spot extraction/modification flow utilizing total NIL simulation is proposed.

Paper Details

Date Published: 19 March 2018
PDF: 7 pages
Proc. SPIE 10584, Novel Patterning Technologies 2018, 105840R (19 March 2018); doi: 10.1117/12.2297361
Show Author Affiliations
Sachiko Kobayashi, Toshiba Corp. (Japan)
Kyoji Yamashita, Toshiba Corp. (Japan)
Hirotaka Tsuda, Toshiba Corp. (Japan)
Kazuhiro Washida, Toshiba Corp. (Japan)
Motofumi Komori, Toshiba Corp. (Japan)
Ji-Young Im, SK Hynix, Inc. (Korea, Republic of)
Takuya Kono, Toshiba Corp. (Japan)
Tetsuro Nakasugi, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 10584:
Novel Patterning Technologies 2018
Eric M. Panning, Editor(s)

© SPIE. Terms of Use
Back to Top