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Improved control of multi-layer overlay in advanced 8nm logic nodes
Author(s): Tae-Sun Kim; Young-Sik Park; Yong-Chul Kim; Byoung-Hoon Kim; Ji-Hun Lee; Min-Keun Kwak; Sung-Won Choi; Joon-Soo Park; Hong-Cheon Yang; Philipp Meixner; Dong-jin Lee; Oh-Sung Kwon; Hyun-Su Kim; Jin-Tae Park; Sung-Min Lee; Cedric Grouwstra; Vidar van der Meijden; Mohamed El Kodadi; Chris Kim; Pierre-Yves Guittet; Tjitte Nooitgedagt
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Paper Abstract

With the increase of litho-etch steps the industry requires metrology to deliver solutions to improve throughput of overlay measurements without impacting accuracy. ASML’s YieldStar 350E is capable of utilizing targets, which can measure the overlay of multiple layers simultaneously. For the work discussed in this paper, an evaluation is performed on Logic product wafers using both single-layer and multi-layer (MLT) quad type targets (able to capture up to four litho-etch steps). Different target types were compared in terms of Move-and-Acquire (MA) time, residual and matching to SEM. Using the MLT targets, an MA time improvement of 56% was demonstrated on the singlelayer. The maximum delta between the overlay residual among the YieldStar targets after applying an high order model was shown to be 0.05 nm. In comparison to after-etch overlay, the correlation of the MLT target was determined with an R2 >; 0.95 using a set-get wafer with induced 10 nm overlay range. On a normal production wafer, the correlation was R2 > 0.67, which is high on a wafer without induced overlay. The comparison of modeling parameters between SEM and MLT targets shows a good match (< 0.16nm) as well.

Paper Details

Date Published: 13 March 2018
PDF: 6 pages
Proc. SPIE 10585, Metrology, Inspection, and Process Control for Microlithography XXXII, 1058527 (13 March 2018); doi: 10.1117/12.2297099
Show Author Affiliations
Tae-Sun Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Young-Sik Park, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Yong-Chul Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Byoung-Hoon Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Ji-Hun Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Min-Keun Kwak, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Sung-Won Choi, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Joon-Soo Park, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Hong-Cheon Yang, ASML Korea Co., Ltd. (Korea, Republic of)
Philipp Meixner, ASML Korea Co., Ltd. (Korea, Republic of)
Dong-jin Lee, ASML Korea Co., Ltd. (Korea, Republic of)
Oh-Sung Kwon, ASML Korea Co., Ltd. (Korea, Republic of)
Hyun-Su Kim, ASML Korea Co., Ltd. (Korea, Republic of)
Jin-Tae Park, ASML Korea Co., Ltd. (Korea, Republic of)
Sung-Min Lee, ASML Korea Co., Ltd. (Korea, Republic of)
Cedric Grouwstra, ASML Netherlands B.V. (Netherlands)
Vidar van der Meijden, ASML Netherlands B.V. (Netherlands)
Mohamed El Kodadi, ASML Netherlands B.V. (Netherlands)
Chris Kim, ASML Netherlands B.V. (Netherlands)
Pierre-Yves Guittet, ASML Netherlands B.V. (Netherlands)
Tjitte Nooitgedagt, ASML Netherlands B.V. (Netherlands)


Published in SPIE Proceedings Vol. 10585:
Metrology, Inspection, and Process Control for Microlithography XXXII
Vladimir A. Ukraintsev, Editor(s)

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