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Proceedings Paper

Low-latency optical parallel adder based on a binary decision diagram with wavelength division multiplexing scheme
Author(s): A. Shinya; T. Ishihara; K. Inoue; K. Nozaki; S. Kita; M. Notomi
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Paper Abstract

We propose an optical parallel adder based on a binary decision diagram that can calculate simply by propagating light through electrically controlled optical pass gates. The CARRY and CARRY operations are multiplexed in one circuit by a wavelength division multiplexing scheme to reduce the number of optical elements, and only a single gate constitutes the critical path for one digit calculation. The processing time reaches picoseconds per digit when we use a 100-μm-long optical path gates, which is ten times faster than a CMOS circuit.

Paper Details

Date Published: 14 February 2018
PDF: 6 pages
Proc. SPIE 10551, Optical Data Science: Trends Shaping the Future of Photonics, 1055106 (14 February 2018); doi: 10.1117/12.2296842
Show Author Affiliations
A. Shinya, NTT Basic Research Labs. (Japan)
T. Ishihara, Kyoto Univ. (Japan)
K. Inoue, Kyushu Univ. (Japan)
K. Nozaki, NTT Basic Research Labs. (Japan)
S. Kita, NTT Basic Research Labs. (Japan)
M. Notomi, NTT Basic Research Labs. (Japan)


Published in SPIE Proceedings Vol. 10551:
Optical Data Science: Trends Shaping the Future of Photonics
Bahram Jalali; Ken-ichi Kitayama; Ata Mahjoubfar, Editor(s)

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