Share Email Print
cover

Proceedings Paper

A low-latency optical switch architecture using integrated um SOI-based contention resolution and switching
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy- and latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-and-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.

Paper Details

Date Published: 22 February 2018
PDF: 5 pages
Proc. SPIE 10538, Optical Interconnects XVIII, 1053808 (22 February 2018); doi: 10.1117/12.2289920
Show Author Affiliations
G. Mourgias-Alexandris, Aristotle Univ. of Thessaloniki (Greece)
M. Moralis-Pegios, Aristotle Univ. of Thessaloniki (Greece)
N. Terzenidis, Aristotle Univ. of Thessaloniki (Greece)
M. Cherchi, VTT Technical Research Ctr. of Finland (Finland)
M. Harjanne, VTT Technical Research Ctr. of Finland (Finland)
T. Aalto, VTT Technical Research Ctr. of Finland (Finland)
K. Vyrsokinos, Aristotle Univ. of Thessaloniki (Greece)
N. Pleros, Aristotle Univ. of Thessaloniki (Greece)


Published in SPIE Proceedings Vol. 10538:
Optical Interconnects XVIII
Henning Schröder; Ray T. Chen, Editor(s)

© SPIE. Terms of Use
Back to Top