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Proceedings Paper

Estimating the circuit delay of FPGA with a transfer learning method
Author(s): Xiuhai Cui; Datong Liu; Yu Peng; Xiyuan Peng
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Paper Abstract

With the increase of FPGA (Field Programmable Gate Array, FPGA) functionality, FPGA has become an on-chip system platform. Due to increase the complexity of FPGA, estimating the delay of FPGA is a very challenge work. To solve the problems, we propose a transfer learning estimation delay (TLED) method to simplify the delay estimation of different speed grade FPGA. In fact, the same style different speed grade FPGA comes from the same process and layout. The delay has some correlation among different speed grade FPGA. Therefore, one kind of speed grade FPGA is chosen as a basic training sample in this paper. Other training samples of different speed grade can get from the basic training samples through of transfer learning. At the same time, we also select a few target FPGA samples as training samples. A general predictive model is trained by these samples. Thus one kind of estimation model is used to estimate different speed grade FPGA circuit delay. The framework of TRED includes three phases: 1) Building a basic circuit delay library which includes multipliers, adders, shifters, and so on. These circuits are used to train and build the predictive model. 2) By contrasting experiments among different algorithms, the forest random algorithm is selected to train predictive model. 3) The target circuit delay is predicted by the predictive model.

The Artix-7, Kintex-7, and Virtex-7 are selected to do experiments. Each of them includes -1, -2, -2l, and -3 different speed grade. The experiments show the delay estimation accuracy score is more than 92% with the TLED method. This result shows that the TLED method is a feasible delay assessment method, especially in the high-level synthesis stage of FPGA tool, which is an efficient and effective delay assessment method.

Paper Details

Date Published: 24 October 2017
PDF: 6 pages
Proc. SPIE 10458, AOPC 2017: 3D Measurement Technology for Intelligent Manufacturing, 104581U (24 October 2017); doi: 10.1117/12.2285825
Show Author Affiliations
Xiuhai Cui, Harbin Institute of Technology (China)
Datong Liu, Harbin Institute of Technology (China)
Yu Peng, Harbin Institute of Technology (China)
Xiyuan Peng, Harbin Institute of Technology (China)

Published in SPIE Proceedings Vol. 10458:
AOPC 2017: 3D Measurement Technology for Intelligent Manufacturing
Wolfgang Osten; Anand Krishna Asundi; Huijie Zhao, Editor(s)

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