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Improved analysis of CMOS photodiode
Author(s): Ji Soo Lee
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Paper Abstract

Presently, various aspects of CMOS technology scaling present additional challenges in CMOS image sensor design. Designers require optical as well as electrical models of the CMOS based pixels and the pixel arrays in order to translate given design objectives to proper choices of technology, pixel architecture, array structure, design layout, etc. Toward this end, we present a one-dimensional analysis and a working model of CMOS photodiode emphasizing on the effect of the finite epitaxial thickness and the presence of electric field at the interface between the epitaxial layer and the substrate bulk.

Paper Details

Date Published: 29 August 2017
PDF: 3 pages
Proc. SPIE 10313, Opto-Canada: SPIE Regional Meeting on Optoelectronics, Photonics, and Imaging, 1031341 (29 August 2017); doi: 10.1117/12.2283941
Show Author Affiliations
Ji Soo Lee, Univ. of Waterloo (Canada)


Published in SPIE Proceedings Vol. 10313:
Opto-Canada: SPIE Regional Meeting on Optoelectronics, Photonics, and Imaging
John C. Armitage, Editor(s)

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