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Proceedings Paper

Small-area vertical thin film transistor in amorphous silicon technology for high pixel fill factor and packing density
Author(s): Isaac Chan
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Paper Abstract

The channel length in conventional TFTs (see Fig. 1), which is defmed by photolithography, is subject to errors associated with masking and etching. Additionally, each of the metallization regions occupies approximately an equal part of the TFT area, thus consuming considerable device area. In contrast, the channel length in vertical TFTs (Fig. 1) is defmed by the thickness of the dielectric layer separating the source and the drain, thus enabling sub-micron channel TFT process with no photolithographic constraints.1,23A5 By orienting the metallization regions vertically, the VTFT area can be reduced down to 1/3 of the conventional TFT area based on the same design rules. When incorporated as switching devices in active matrix liquid crystal displays or active matrix flat panel imagers, a considerable reduction in pixel size can be achieved.

Paper Details

Date Published: 29 August 2017
PDF: 3 pages
Proc. SPIE 10313, Opto-Canada: SPIE Regional Meeting on Optoelectronics, Photonics, and Imaging, 103133Z (29 August 2017); doi: 10.1117/12.2283939
Show Author Affiliations
Isaac Chan, Univ. of Waterloo (Canada)

Published in SPIE Proceedings Vol. 10313:
Opto-Canada: SPIE Regional Meeting on Optoelectronics, Photonics, and Imaging
John C. Armitage, Editor(s)

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