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Proceedings Paper

Adopting rigorous verification flow in fabrication of silicon photonic devices
Author(s): Siti Noor Aisyah Binti Yahya; Mogana Sundharam A/L Sathisivan; Chuanhai Li; Jinhua Pei; Yu Chen
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Paper Abstract

Throughout this report, we demonstrate the benefits of lithography simulation for the fabrication of the photonic devices using a rigorous verification flow. In our case, we report the application rigorous lithography simulation to predict the fabrication imperfections of silicon photonic devices during the lithography process. Resist calibration has been performed, with both FEM CD and resist profile simulation results matching well with the wafer results for the design rule patterns. SEM overlay proves that the simulation contours agree with the wafer images for the design rule test patterns.

Paper Details

Date Published: 16 October 2017
PDF: 11 pages
Proc. SPIE 10451, Photomask Technology, 1045106 (16 October 2017); doi: 10.1117/12.2280485
Show Author Affiliations
Siti Noor Aisyah Binti Yahya, Silterra Malaysia Sdn. Bhd. (Malaysia)
Mogana Sundharam A/L Sathisivan, Silterra Malaysia Sdn. Bhd. (Malaysia)
Chuanhai Li, Synopsys (Singapore) Pte. Ltd. (Singapore)
Jinhua Pei, Synopsys (Shanghai) Co. Ltd. (China)
Yu Chen, Synopsys (Shanghai) Co. Ltd. (China)


Published in SPIE Proceedings Vol. 10451:
Photomask Technology
Peter D. Buck; Emily E. Gallagher, Editor(s)

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