Share Email Print
cover

Proceedings Paper • new

Reducing hardware in FPGA-based Mealy FSM
Author(s): Małgorzata Kołopieńczyk; Larysa Titarenko; Kamil Mielcarek; Alexander Barkalov
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This article is devoted to design of Mealy FSM with FPGAs using embedded memory blocks and look-up table elements. There is presented the state-of-the-art. The method is proposed for design of Mealy FSM logic circuit with embedded memory blocks based on encoding of collections of outputs and replacement of inputs. Example of design and research results are given.

Paper Details

Date Published: 7 August 2017
PDF: 12 pages
Proc. SPIE 10445, Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017, 104451G (7 August 2017); doi: 10.1117/12.2280407
Show Author Affiliations
Małgorzata Kołopieńczyk, Univ. of Zielona Góra (Poland)
Larysa Titarenko, Univ. of Zielona Góra (Poland)
Kamil Mielcarek, Univ. of Zielona Góra (Poland)
Alexander Barkalov, Univ. of Zielona Góra (Poland)


Published in SPIE Proceedings Vol. 10445:
Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017
Ryszard S. Romaniuk; Maciej Linczuk, Editor(s)

© SPIE. Terms of Use
Back to Top