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Proceedings Paper

Digital cyphering system using chaos time series
Author(s): Hajime Takakubo; Katsufusa Shono
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Paper Abstract

A voltage-mode CMOS looped circuit generates complex chaos time series, and it is digitized by an AD converter. The digitized time series of internal state shows an irreversible multiple complexity in the past, due to bifurcation. The multiple complexity of internal states in chaos time series is utilized as a scramble code in a digital ciphering system. A binary coded information is bit-serially converted into a corresponding scramble code. An average conversion rate of the ciphering system using 8-bit data base is 102 k bit/sec. On the other hand, the internal states in the future time series are quite deterministic, even if it has multiple internal states in the past. The scramble code can be decoded by the deterministic phenomenon.

Paper Details

Date Published: 1 December 1995
PDF: 12 pages
Proc. SPIE 2612, Chaotic Circuits for Communication, (1 December 1995); doi: 10.1117/12.227905
Show Author Affiliations
Hajime Takakubo, Sophia Univ. (Japan)
Katsufusa Shono, Sophia Univ. (Japan)

Published in SPIE Proceedings Vol. 2612:
Chaotic Circuits for Communication
Jaafar M. H. Elmirghani, Editor(s)

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