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Proceedings Paper

Spintronics: a potential pathway to enable an exponential scaling for beyond-CMOS era (Conference Presentation)
Author(s): Jian-Ping Wang
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Paper Abstract

Many key technologies of our society, including artificial intelligence (AI) and big data, have been enabled by the invention of transistor and its ever-decreasing size and ever-increasing integration at a large scale. There is a clear scaling limit to the conventional transistor technology, however. Many recently proposed advanced transistors are also having an uphill fight in lab because of necessary performance tradeoffs and limited scaling potential. In this talk, we argue for a new pathway that could enable exponential scaling for multiple generations. This pathway involves layering multiple technologies that are beyond the available functions of conventional and newly proposed transistors. We believe that this potential pathway is becoming clear through recent worldwide effort. In this talk, I will brief you my group’s recent progress on two selected topics along this line, one on the STT-RAM and one on spin logic. Meanwhile I will also introduce a team effort of C-SPIN Center of STARnet program, where systems designers, devices builders, materials scientists and physicist all work under one roof to tackle the scaling issue and overcome key technology barriers. Several successful examples such as the logic in memory, cognitive computing, probabilistic computing and reconfigurable information processing will be discussed.

Paper Details

Date Published: 11 October 2017
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Proc. SPIE 10357, Spintronics X, 103570L (11 October 2017); doi: 10.1117/12.2278745
Show Author Affiliations
Jian-Ping Wang, Univ. of Minnesota (United States)


Published in SPIE Proceedings Vol. 10357:
Spintronics X
Henri-Jean Drouhin; Jean-Eric Wegrowe; Manijeh Razeghi; Henri Jaffrès, Editor(s)

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