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Scalable maskless patterning of nanostructures using high-speed scanning probe arrays
Author(s): Chen Chen; Meghana Akella; Zhidong Du; Liang Pan
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Paper Abstract

Nanoscale patterning is the key process to manufacture important products such as semiconductor microprocessors and data storage devices. Many studies have shown that it has the potential to revolutionize the functions of a broad range of products for a wide variety of applications in energy, healthcare, civil, defense and security. However, tools for mass production of these devices usually cost tens of million dollars each and are only affordable to the established semiconductor industry. A new method, nominally known as "pattern-on-the- y", that involves scanning an array of optical or electrical probes at high speed to form nanostructures and offers a new low-cost approach for nanoscale additive patterning. In this paper, we report some progress on using this method to pattern self-assembled monolayers (SAMs) on silicon substrate. We also functionalize the substrate with gold nanoparticle based on the SAM to show the feasibility of preparing amphiphilic and multi-functional surfaces.

Paper Details

Date Published: 31 August 2017
PDF: 4 pages
Proc. SPIE 10354, Nanoengineering: Fabrication, Properties, Optics, and Devices XIV, 103540E (31 August 2017); doi: 10.1117/12.2273546
Show Author Affiliations
Chen Chen, Purdue Univ. (United States)
Meghana Akella, Iowa State Univ. (United States)
Zhidong Du, Purdue Univ. (United States)
Liang Pan, Purdue Univ. (United States)


Published in SPIE Proceedings Vol. 10354:
Nanoengineering: Fabrication, Properties, Optics, and Devices XIV
Eva M. Campo; Elizabeth A. Dobisz; Louay A. Eldada, Editor(s)

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