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Proceedings Paper

A 10 Gs/s latched comparator with dynamic offset cancellation in 28nm FD-SOI process
Author(s): Zbigniew Jaworski
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Paper Abstract

This papers presents a high-speed, latched comparator implemented in industrial 28 nm FD-SOI technology. A novel approach to counter the mismatch is proposed. The solution employs trimming the threshold voltage by means of modulating of back-gate polarization of FD-SOI transistors. The comparator is a first step towards the design of a complete 4-bit FLASH analog-to-digital converter, with a sampling frequency of 10 GHz.

Paper Details

Date Published: 22 December 2016
PDF: 7 pages
Proc. SPIE 10175, Electron Technology Conference 2016, 101750A (22 December 2016); doi: 10.1117/12.2263521
Show Author Affiliations
Zbigniew Jaworski, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 10175:
Electron Technology Conference 2016
Barbara Swatowska; Wojciech Maziarz; Tadeusz Pisarkiewicz; Wojciech Kucewicz, Editor(s)

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