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Proceedings Paper

Pattern-based analytics to estimate and track yield risk of designs down to 7nm
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Paper Abstract

Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with respect to previous generations is made. In addition to identifying topological patterns that are unique to a particular design, novel techniques are proposed for scoring those patterns based on potential yield risk factors to find patterns that pose the highest risk.

Paper Details

Date Published: 30 March 2017
PDF: 14 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014805 (30 March 2017); doi: 10.1117/12.2262363
Show Author Affiliations
Jason P. Cain, Advanced Micro Devices, Inc. (United States)
Moutaz Fakhry, Advanced Micro Devices, Inc. (United States)
Piyush Pathak, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Frank E. Gennari, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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