Share Email Print
cover

Proceedings Paper

Optimization of complex high-dimensional layout configurations for IC physical designs using graph search, data analytics, and machine learning
Author(s): Vito Dai; Edward Kah Ching Teoh; Ji Xu; Bharath Rangarajan
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

A typical new IC design has millions of layout configurations, not seen on previous product or test chip designs. Knowing the disposition of each and every configuration, problematic or not, is the key to optimizing design for yield. In this paper, we present a method to systematically characterize the configuration coverage of any layout. Coverage can be compared between designs, and configurations for which there is a lack of coverage can also be computed. When combined with simulation, metrology, and defect data for some configurations, graph search and machine learning algorithms can be applied to optimize designs for manufacturing yield.

Paper Details

Date Published: 3 April 2017
PDF: 9 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014808 (3 April 2017); doi: 10.1117/12.2262146
Show Author Affiliations
Vito Dai, Motivo, Inc. (United States)
Edward Kah Ching Teoh, Motivo, Inc. (United States)
Ji Xu, Motivo, Inc. (United States)
Bharath Rangarajan, Motivo, Inc. (United States)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

© SPIE. Terms of Use
Back to Top