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Proceedings Paper

CMOS standard cells characterization for open defects for test pattern generation
Author(s): Andrzej Wielgus; Witold Pleskacz
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Paper Abstract

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. It allows to estimate the probabilities of physical open defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, the minimal set of test sequences is selected to cover all detectable faults and the optimal complex test sequence is constructed. Experimental results for cells from industrial standard cell library are presented as well.

Paper Details

Date Published: 22 December 2016
PDF: 8 pages
Proc. SPIE 10175, Electron Technology Conference 2016, 101750I (22 December 2016); doi: 10.1117/12.2261887
Show Author Affiliations
Andrzej Wielgus, Warsaw Univ. of Technology (Poland)
Witold Pleskacz, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 10175:
Electron Technology Conference 2016
Barbara Swatowska; Wojciech Maziarz; Tadeusz Pisarkiewicz; Wojciech Kucewicz, Editor(s)

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