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Proceedings Paper

Quantifying electrical impacts on redundant wire insertion in 7nm unidirectional designs
Author(s): Ahmed Mohyeldin; Uwe Paul Schroeder; Ramya Srinivasan; Haritez Narisetty; Shobhit Malik; Sriram Madhavan
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Paper Abstract

In nano-meter scale Integrated Circuits, via fails due to random defects is a well-known yield detractor, and via redundancy insertion is a common method to help enhance semiconductors yield. For the case of Self Aligned Double Patterning (SADP), which might require unidirectional design layers as in the case of some advanced technology nodes, the conventional methods of inserting redundant vias don’t work any longer. This is because adding redundant vias conventionally requires adding metal shapes in the non-preferred direction, which will violate the SADP design constraints in that case. Therefore, such metal layers fabricated using unidirectional SADP require an alternative method for providing the needed redundancy.

This paper proposes a post-layout Design for Manufacturability (DFM) redundancy insertion method tailored for the design requirements introduced by unidirectional metal layers. The proposed method adds redundant wires in the preferred direction - after searching for nearby vacant routing tracks - in order to provide redundant paths for electrical signals. This method opportunistically adds robustness against failures due to silicon defects without impacting area or incurring new design rule violations. Implementation details of this redundancy insertion method will be explained in this paper.

One known challenge with similar DFM layout fixing methods is the possible introduction of undesired electrical impact, causing other unintentional failures in design functionality. In this paper, a study is presented to quantify the electrical impacts of such redundancy insertion scheme and to examine if that electrical impact can be tolerated. The paper will show results to evaluate DFM insertion rates and corresponding electrical impact for a given design utilization and maximum inserted wire length. Parasitic extraction and static timing analysis results will be presented. A typical digital design implemented using GLOBALFOUNDRIES 7nm technology is used for demonstration.

The provided results can help evaluate such extensive DFM insertion method from an electrical standpoint. Furthermore, the results could provide guidance on how to implement the proposed method of adding electrical redundancy such that intolerable electrical impacts could be avoided.

Paper Details

Date Published: 3 April 2017
PDF: 13 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480N (3 April 2017); doi: 10.1117/12.2261588
Show Author Affiliations
Ahmed Mohyeldin, GLOBALFOUNDRIES Inc. (United States)
Uwe Paul Schroeder, GLOBALFOUNDRIES Inc. (United States)
Ramya Srinivasan, GLOBALFOUNDRIES Inc. (United States)
Haritez Narisetty, GLOBALFOUNDRIES Inc. (United States)
Shobhit Malik, GLOBALFOUNDRIES Inc. (United States)
Sriram Madhavan, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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