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Proceedings Paper

Patterning control strategies for minimum edge placement error in logic devices
Author(s): Jan Mulkens; Michael Hanna; Bram Slachter; Wim Tel; Michael Kubis; Mark Maslow; Chris Spence; Vadim Timoshkov
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Paper Abstract

In this paper we discuss the edge placement error (EPE) for multi-patterning semiconductor manufacturing. In a multi-patterning scheme the creation of the final pattern is the result of a sequence of lithography and etching steps, and consequently the contour of the final pattern contains error sources of the different process steps. We describe the fidelity of the final pattern in terms of EPE, which is defined as the relative displacement of the edges of two features from their intended target position. We discuss our holistic patterning optimization approach to understand and minimize the EPE of the final pattern. As an experimental test vehicle we use the 7-nm logic device patterning process flow as developed by IMEC. This patterning process is based on Self-Aligned-Quadruple-Patterning (SAQP) using ArF lithography, combined with line cut exposures using EUV lithography. The computational metrology method to determine EPE is explained. It will be shown that ArF to EUV overlay, CDU from the individual process steps, and local CD and placement of the individual pattern features, are the important contributors. Based on the error budget, we developed an optimization strategy for each individual step and for the final pattern. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets.

Paper Details

Date Published: 28 March 2017
PDF: 13 pages
Proc. SPIE 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 1014505 (28 March 2017); doi: 10.1117/12.2260155
Show Author Affiliations
Jan Mulkens, ASML Netherlands B.V. (Netherlands)
Michael Hanna, ASML USA, Inc. (United States)
Bram Slachter, ASML Netherlands B.V. (Netherlands)
Wim Tel, ASML Netherlands B.V. (Netherlands)
Michael Kubis, ASML Netherlands B.V. (Netherlands)
Mark Maslow, ASML Netherlands B.V. (Netherlands)
Chris Spence, ASML Silicon Valley (United States)
Vadim Timoshkov, ASML Netherlands B.V. (Netherlands)


Published in SPIE Proceedings Vol. 10145:
Metrology, Inspection, and Process Control for Microlithography XXXI
Martha I. Sanchez, Editor(s)

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