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Proceedings Paper

SOCS based post-layout optimization for multiple patterns with light interference prediction
Author(s): Taiki Kimura; Tetsuaki Matsunawa; Shigeki Nojima; David Z. Pan
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Paper Abstract

As technology node shrinks down, hotspots, i.e. patterning failures on wafer after etching process, become an inevitable problem. The main cause of such hotspots is low contrast of aerial image. There are several methods that can improve aerial image contrast such as SRAF insertion and OPC. However, it is difficult to fix all hotspots by applying only SRAF and OPC in advanced technology node. This paper proposes a new post-layout optimization method, before SRAF and OPC, based on SOCS kernel for improving aerial image contrast and reducing hotspots. Experimental results show average 4nm PV-band improvement, as a result of contrast improvement.

Paper Details

Date Published: 30 March 2017
PDF: 7 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480A (30 March 2017); doi: 10.1117/12.2260091
Show Author Affiliations
Taiki Kimura, Toshiba Corp. (Japan)
Tetsuaki Matsunawa, Toshiba Corp. (Japan)
Shigeki Nojima, Toshiba Corp. (Japan)
David Z. Pan, The Univ. of Texas at Austin (United States)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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