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Advanced in-production hotspot prediction and monitoring with micro-topography
Author(s): P. Fanton; T. Hasan; A. Lakcher; B. Le-Gratiet; C. Prentice; J.-G. Simiz; R. La Greca; L. Depre; S. Hunsche
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Paper Abstract

At 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical to prevent hotspots from becoming yield-limiting defects. We previously established proof of concept for a systematic approach to identify the most critical pattern locations, i.e. hotspots, in a reticle layout by computational lithography and combining process window characteristics of these patterns with across-wafer process variation data to predict where hotspots may become yield impacting defects [1,2]. The current paper establishes the impact of micro-topography on a 28nm metal layer, and its correlation with hotspot best focus variations across a production chip layout. Detailed topography measurements are obtained from an offline tool, and pattern-dependent best focus (BF) shifts are determined from litho simulations that include mask-3D effects. We also establish hotspot metrology and defect verification by SEM image contour extraction and contour analysis. This enables detection of catastrophic defects as well as quantitative characterization of pattern variability, i.e. local and global CD uniformity, across a wafer to establish hotspot defect and variability maps. Finally, we combine defect prediction and verification capabilities for process monitoring by on-product, guided hotspot metrology, i.e. with sampling locations being determined from the defect prediction model and achieved prediction accuracy (capture rate) around 75%

Paper Details

Date Published: 28 March 2017
PDF: 10 pages
Proc. SPIE 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 101450X (28 March 2017); doi: 10.1117/12.2260024
Show Author Affiliations
P. Fanton, STMicroelectronics (France)
T. Hasan, ASML US, Inc. (United States)
A. Lakcher, STMicroelectronics (France)
Lab. des Technologies de la Microélectronique, CNRS (France)
B. Le-Gratiet, STMicroelectronics (France)
C. Prentice, ASML SARL (France)
J.-G. Simiz, STMicroelectronics (France)
R. La Greca, ASML SARL (France)
L. Depre, ASML SARL (France)
S. Hunsche, ASML US, Inc. (United States)


Published in SPIE Proceedings Vol. 10145:
Metrology, Inspection, and Process Control for Microlithography XXXI
Martha I. Sanchez, Editor(s)

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