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Exploiting regularity: breakthroughs in sub-7nm place-and-route
Author(s): L. Liebmann; V. Gerousis; Paul Gutwin; Xuelian Zhu; Jan Petykiewicz
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Paper Abstract

As pitch scaling is becoming constrained not only by lithographic resolution limits but alos by fundamental device and interconnect challenges the semiconductor industry has turned to cell-height reduction as a means of achieving competitive area scaling. The risk in using cell-height reduction to compensate for insufficient pitch scaling is that place- and-route inefficiencies caused by wiring congestion at the block level of the design can easily eliminate any area scaling gains made at the cell level of the design. This paper shows how careful cell-architecture optimization, physical design methodology changes, and place-and-route innovations have led to competitive block level area scaling for 7nm technology nodes and beyond. Data is presented to show that an entire node’s worth of scaling can be achieved through these comprehensive design-technology co-optimization efforts.

Paper Details

Date Published: 28 March 2017
PDF: 10 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480F (28 March 2017); doi: 10.1117/12.2259981
Show Author Affiliations
L. Liebmann, GLOBALFOUNDRIES Inc. (United States)
V. Gerousis, Cadence Design Systems, Inc. (United States)
Paul Gutwin, Cadence Design Systems, Inc. (United States)
Xuelian Zhu, GLOBALFOUNDRIES Inc. (United States)
Jan Petykiewicz, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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