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A pattern-based design analysis method by using inline inspection data more efficiently
Author(s): Linda Zhuang; Annie Zhu; Yifan Zhang; Jason Sweis; Ya-Chieh Lai
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Paper Abstract

The IC chip manufacturing process is an integrated working flow where after each manufacturing step, a yield inspection team will apply great effort and machine resources to inspect and sort through various check points to detect silicon failures. However, despite the great effort, they cannot efficiently cover a whole chip and cross check all the different layers and products at the same time.

This paper will present a smart and efficient working flow that can map inspection data back onto a design and produce more diverse monitor points for inspection, and each set of monitor points links to a set of statistical design data that shows insight on design structures that are more sensitive to the process variations. A full-chip post-processing flow is also implemented to process design layout so that the particular patterns that may cause certain function blocks to fail can be directly checked on post-processed layout.

Paper Details

Date Published: 28 March 2017
PDF: 6 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480X (28 March 2017); doi: 10.1117/12.2259936
Show Author Affiliations
Linda Zhuang, Semiconductor Manufacturing International Corp. (China)
Annie Zhu, Semiconductor Manufacturing International Corp. (China)
Yifan Zhang, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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