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Proceedings Paper

Computational scanner wafer mark alignment
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Paper Abstract

In the process nodes of 10nm and below, the patterning complexity, along with multiple pattern processing and the advance materials required, has in turn resulted in a need to optimize wafer alignment mark simulation capabilities in order to achieve the required precision and accuracy for wafer alignment performance.

ASML’s Design for Control (D4C) application for wafer alignment mark design has been extended to support the computational prediction of alignment mark performance for the latest alignment sensor on the TwinScan NXT:1980Di platform and beyond. Additional new simulation functionality will also be introduced to enable aberration sensitivity matching between the alignment mark and the device cell patterns. As a result, the design of more robust alignment marks is achieved, extending simulation capabilities for the design of wafer alignment marks and the recommendation of alignment recipe settings.

Paper Details

Date Published: 30 March 2017
PDF: 9 pages
Proc. SPIE 10147, Optical Microlithography XXX, 101471C (30 March 2017); doi: 10.1117/12.2259750
Show Author Affiliations
Boris Menchtchikov, ASML Brion (United States)
Robert Socha, ASML Brion (United States)
Sudharshanan Raghunathan, ASML Brion (United States)
Irina Lyulina, ASML Brion (United States)
Hielke Schoonewelle, ASML Netherlands B.V. (Netherlands)
Patrick Tinnemans, ASML Netherlands B.V. (Netherlands)
Paul Tuffy, ASML Netherlands B.V. (Netherlands)
Philippe Leray, IMEC (Belgium)
Christiane Jehoul, IMEC (Belgium)


Published in SPIE Proceedings Vol. 10147:
Optical Microlithography XXX
Andreas Erdmann; Jongwook Kye, Editor(s)

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