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Proceedings Paper

Advanced application of pattern-aware OPC
Author(s): James Chen; Shin-Shing Yeh; Alan Zhu; Bayram Yenikaya; Fan-Hsuan Hsu; Yung-Ching Mai; Lawrence Lin; Nelson Lai
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Paper Abstract

For advanced technology nodes, it’s critical to address yield issues caused by process specific layout patterns with limited process window. RETs such as Model-Based Sub-Resolution Assist Feature (MB-SRAF) are introduced to guarantee high lithographic margin, but these techniques come with long runtime, especially when applied full-chip. There’s also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process.

In this paper, we introduce a flow that applies advanced RET such as MBSRAF or specific local corrections to layouts with critical and yield limiting patterns. We also introduce in-process pattern match based on Cadence topological Squish pattern. Overall, this new flow of Pattern-Aware OPC (PA-OPC) achieves better margin for hotspots, without sacrificing turnaround time and is able to handle more complex patterns and environment than traditional methods. We demonstrate the benefit of the new flow with fine-grained process window control over different patterns.

Paper Details

Date Published: 24 March 2017
PDF: 9 pages
Proc. SPIE 10147, Optical Microlithography XXX, 101471W (24 March 2017); doi: 10.1117/12.2258331
Show Author Affiliations
James Chen, Cadence Design Systems, Inc. (Taiwan)
Shin-Shing Yeh, Powerchip Technology Corp. (Taiwan)
Alan Zhu, Cadence Design Systems, Inc. (United States)
Bayram Yenikaya, Cadence Design Systems, Inc. (United States)
Fan-Hsuan Hsu, Powerchip Technology Corp. (Taiwan)
Yung-Ching Mai, Powerchip Technology Corp. (Taiwan)
Lawrence Lin, Powerchip Technology Corp. (Taiwan)
Nelson Lai, Powerchip Technology Corp. (Taiwan)


Published in SPIE Proceedings Vol. 10147:
Optical Microlithography XXX
Andreas Erdmann; Jongwook Kye, Editor(s)

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