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Proceedings Paper

Optimize of shrink process with X-Y CD bias on hole pattern
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Paper Abstract

Gridded design rules[1] is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line and space pattern by using multiple patterning techniques such as self-aligned multiple patterning (SAMP) and litho-etch- litho-etch (LELE)[2][3][4] . On the other hand, Line cut process has some error parameters such as pattern defect, placement error, roughness and X-Y CD bias with the decreasing scale. We tried to cure hole pattern roughness to use additional process such as Line smoothing[5] . Each smoothing process showed different effect. As the result, CDx shrink amount is smaller than CDy without one additional process. In this paper, we will report the pattern controllability comparison of EUV and 193-immersion. And we will discuss optimum method about CD bias on hole pattern.

Paper Details

Date Published: 27 March 2017
PDF: 8 pages
Proc. SPIE 10146, Advances in Patterning Materials and Processes XXXIV, 101461N (27 March 2017); doi: 10.1117/12.2258221
Show Author Affiliations
Kyohei Koike, Tokyo Electron Yamanashi Ltd. (Japan)
Arisa Hara, Tokyo Electron Yamanashi Ltd. (Japan)
Sakurako Natori, Tokyo Electron Yamanashi Ltd. (Japan)
Shohei Yamauchi, Tokyo Electron Yamanashi Ltd. (Japan)
Masatoshi Yamato, Tokyo Electron Yamanashi Ltd. (Japan)
Kenichi Oyama, Tokyo Electron Yamanashi Ltd. (Japan)
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)


Published in SPIE Proceedings Vol. 10146:
Advances in Patterning Materials and Processes XXXIV
Christoph K. Hohle, Editor(s)

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