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Proceedings Paper

User-friendly design approach for analog layout design
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Paper Abstract

Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing processes, and variations. This paper presents analog verification flow with five types of analogfocused layout constraint checks to assist engineers in identifying any potential device mismatch and layout drawing mistakes. Compared to several solutions, our approach only requires layout design, which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation and allows seamless integration into the layout environment with minimum disruption to the custom layout flow. Our user-friendly analog verification flow provides the engineer with more confident with their layouts quality.

Paper Details

Date Published: 28 March 2017
PDF: 13 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014814 (28 March 2017); doi: 10.1117/12.2258203
Show Author Affiliations
Yongfu Li, GLOBALFOUNDRIES Singapore (Singapore)
Zhao Chuan Lee, GLOBALFOUNDRIES Singapore (Singapore)
Vikas Tripathi, GLOBALFOUNDRIES Singapore (Singapore)
Valerio Perez, GLOBALFOUNDRIES Singapore (Singapore)
Yoong Seang Ong, GLOBALFOUNDRIES Singapore (Singapore)
Chiu Wing Hui, GLOBALFOUNDRIES Singapore (Singapore)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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