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Proceedings Paper

Pattern optimizing verification of self-align quadruple patterning
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Paper Abstract

Lithographic scaling continues to advance by extending the life of 193nm immersion technology, and spacer-type multi-patterning is undeniably the driving force behind this trend. Multi-patterning techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) have come to be used in memory devices, and they have also been adopted in logic devices to create constituent patterns in the formation of 1D layout designs. Multi-patterning has consequently become an indispensible technology in the fabrication of all advanced devices. In general, items that must be managed when using multi-patterning include critical dimension uniformity (CDU), line edge roughness (LER), and line width roughness (LWR). Recently, moreover, there has been increasing focus on judging and managing pattern resolution performance from a more detailed perspective and on making a right/wrong judgment from the perspective of edge placement error (EPE). To begin with, pattern resolution performance in spacer-type multi-patterning is affected by the process accuracy of the core (mandrel) pattern. Improving the controllability of CD and LER of the mandrel is most important, and to reduce LER, an appropriate smoothing technique should be carefully selected. In addition, the atomic layer deposition (ALD) technique is generally used to meet the need for high accuracy in forming the spacer film. Advances in scaling are accompanied by stricter requirements in the controllability of fine processing. In this paper, we first describe our efforts in improving controllability by selecting the most appropriate materials for the mandrel pattern and spacer film. Then, based on the materials selected, we present experimental results on a technique for improving etching selectivity.

Paper Details

Date Published: 5 April 2017
PDF: 8 pages
Proc. SPIE 10146, Advances in Patterning Materials and Processes XXXIV, 101461M (5 April 2017); doi: 10.1117/12.2258154
Show Author Affiliations
Masatoshi Yamato, Tokyo Electron Yamanashi Ltd. (Japan)
Kazuki Yamada, Tokyo Electron Yamanashi Ltd. (Japan)
Kenichi Oyama, Tokyo Electron Yamanashi Ltd. (Japan)
Arisa Hara, Tokyo Electron Yamanashi Ltd. (Japan)
Sakurako Natori, Tokyo Electron Yamanashi Ltd. (Japan)
Shouhei Yamauchi, Tokyo Electron Yamanashi Ltd. (Japan)
Kyohei Koike, Tokyo Electron Yamanashi Ltd. (Japan)
Hidetami Yaegashi, Tokyo Electron Yamanashi Ltd. (Japan)


Published in SPIE Proceedings Vol. 10146:
Advances in Patterning Materials and Processes XXXIV
Christoph K. Hohle, Editor(s)

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