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Proceedings Paper

A random generation approach to pattern library creation for full chip lithographic simulation
Author(s): Elain Zou; Sid Hong; Limei Liu; Lucas Huang; Legender Yang; Aliaa Kabeel; Kareem Madkour; Wael ElManhawy; Joe Kwan; Chunshan Du; Xinyi Hu; Qijian Wan; Recoo Zhang
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Paper Abstract

As technology advances, the need for running lithographic (litho) checking for early detection of hotspots before tapeout has become essential. This process is important at all levels—from designing standard cells and small blocks to large intellectual property (IP) and full chip layouts. Litho simulation provides high accuracy for detecting printability issues due to problematic geometries, but it has the disadvantage of slow performance on large designs and blocks [1]. Foundries have found a good compromise solution for running litho simulation on full chips by filtering out potential candidate hotspot patterns using pattern matching (PM), and then performing simulation on the matched locations. The challenge has always been how to easily create a PM library of candidate patterns that provides both comprehensive coverage for litho problems and fast runtime performance. This paper presents a new strategy for generating candidate real design patterns through a random generation approach using a layout schema generator (LSG) utility. The output patterns from the LSG are simulated, and then classified by a scoring mechanism that categorizes patterns according to the severity of the hotspots, probability of their presence in the design, and the likelihood of the pattern causing a hotspot. The scoring output helps to filter out the yield problematic patterns that should be removed from any standard cell design, and also to define potential problematic patterns that must be simulated within a bigger context to decide whether or not they represent an actual hotspot. This flow is demonstrated on SMIC 14nm technology, creating a candidate hotspot pattern library that can be used in full chip simulation with very high coverage and robust performance.

Paper Details

Date Published: 4 April 2017
PDF: 10 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014811 (4 April 2017); doi: 10.1117/12.2258133
Show Author Affiliations
Elain Zou, Semiconductor Manufacturing International Corp. (China)
Sid Hong, Semiconductor Manufacturing International Corp. (China)
Limei Liu, Semiconductor Manufacturing International Corp. (China)
Lucas Huang, Semiconductor Manufacturing International Corp. (China)
Legender Yang, Semiconductor Manufacturing International Corp. (China)
Aliaa Kabeel, Mentor Graphics Egypt (Egypt)
Kareem Madkour, Mentor Graphics Egypt (Egypt)
Wael ElManhawy, Mentor Graphics Corp. (United States)
Joe Kwan, Mentor Graphics Corp. (United States)
Chunshan Du, Mentor Graphics Corp. (China)
Xinyi Hu, Mentor Graphics Corp. (China)
Qijian Wan, Mentor Graphics Corp. (China)
Recoo Zhang, Mentor Graphics Corp. (China)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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