Share Email Print
cover

Proceedings Paper

Systematic analysis of the timing and power impact of pure lines and cuts routing for multiple patterning
Author(s): Vinay Vashishtha; Lovish Masand; Ankita Dosi; Chandarasekaran Ramamurthy; Lawrence T. Clark
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Line and cut based patterning for BEOL layers is an attractive solution to address the block mask patterning challenges related to self-aligned double patterning. It also enables integrated fill, with fill as an artifact of unused metal routes following lines and cuts patterning. Traditional post-layout fill involves inserting metal at large distances to limit design impact, but is less effective at alleviating metal thickness variation due to density effects. While integrated fill reduces metal thickness variation, it has a negative impact on capacitance, delay and power dissipation. This work studies the impact of pure lines/cuts integrated fill on design performance metrics using a predictive 7 nm PDK.

Two fully implemented auto-place and routed (APR) designs are considered for the experiments, one small and one large. Our comparison is from no fill to integrated fill, assuming conventional fill would not impact timing. The impact of integrated fill on capacitance and overall timing is evaluated using Calibre PEX and PrimeTime. We show these results are in line with simple “back of the envelope” estimates and simple models and are very significant for large designs.

Paper Details

Date Published: 28 March 2017
PDF: 8 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480P (28 March 2017); doi: 10.1117/12.2258085
Show Author Affiliations
Vinay Vashishtha, Arizona State Univ. (United States)
Lovish Masand, Arizona State Univ. (United States)
Ankita Dosi, Arizona State Univ. (United States)
Chandarasekaran Ramamurthy, Arizona State Univ. (United States)
Lawrence T. Clark, Arizona State Univ. (United States)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

© SPIE. Terms of Use
Back to Top