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Proceedings Paper

A fast process development flow by applying design technology co-optimization
Author(s): Yi-Chieh Chen; Shin-Shing Yeh; Tsong-Hua Ou; Hung-Yu Lin; Yung-Ching Mai; Lawrence Lin; Jun-Cheng Lai; Ya Chieh Lai; Wei Xu; Philippe Hurat
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Paper Abstract

Beyond 40 nm technology node, the pattern weak points and hotspot types increase dramatically. The typical patterns for lithography verification suffers huge turn-around-time (TAT) to handle the design complexity. Therefore, in order to speed up process development and increase pattern variety, accurate design guideline and realistic design combinations are required. This paper presented a flow for creating a cell-based layout, a lite realistic design, to early identify problematic patterns which will negatively affect the yield.

A new random layout generating method, Design Technology Co-Optimization Pattern Generator (DTCO-PG), is reported in this paper to create cell-based design. DTCO-PG also includes how to characterize the randomness and fuzziness, so that it is able to build up the machine learning scheme which model could be trained by previous results, and then it generates patterns never seen in a lite design. This methodology not only increases pattern diversity but also finds out potential hotspot preliminarily.

This paper also demonstrates an integrated flow from DTCO pattern generation to layout modification. Optical Proximity Correction, OPC and lithographic simulation is then applied to DTCO-PG design database to detect hotspots and then hotspots or weak points can be automatically fixed through the procedure or handled manually. This flow benefits the process evolution to have a faster development cycle time, more complexity pattern design, higher probability to find out potential hotspots in early stage, and a more holistic yield ramping operation.

Paper Details

Date Published: 28 March 2017
PDF: 7 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014815 (28 March 2017); doi: 10.1117/12.2257973
Show Author Affiliations
Yi-Chieh Chen, Cadence Design Systems, Inc. (Taiwan)
Shin-Shing Yeh, Powerchip Technology Corp. (Taiwan)
Tsong-Hua Ou, Cadence Design Systems, Inc. (Taiwan)
Hung-Yu Lin, Cadence Design Systems, Inc. (Taiwan)
Yung-Ching Mai, Powerchip Technology Corp. (Taiwan)
Lawrence Lin, Powerchip Technology Corp. (Taiwan)
Jun-Cheng Lai, Powerchip Technology Corp. (Taiwan)
Ya Chieh Lai, Cadence Design Systems, Inc. (United States)
Wei Xu, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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