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Proceedings Paper

Improving the topography performance of ion implantation resist
Author(s): Lisong Dong; Wenhui Chen; Xiaojing Su; Yayi Wei
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Paper Abstract

As the fin based field effect transistors (Fin-FET) emerge, the device structure is changed from two dimensional to three dimensional. Due to the existence of topography, the lithographic performance may be affected and, in most cases, becomes more complicated, especially in the ion implantation process after gate being constructed. In this paper, the various parameters that may have influence on the resist topography are being investigated, such as the density, height, and corner rounding of the fin structures, the height, and the corner rounding of the gates, etc. Theoretical analysis shows that the resist image intensity among the fins and gates can be improved by increasing the thickness of the oxide on the edge of the gate. Following the above theoretical analysis, a method for lithographic performance improvement with the existence of resist topography is proposed. The method is demonstrated from the simulations with the lithography simulator PROLITH. With an optimal thickness of oxide on the surface of gate, the residual resist in the topography after development will be removed thoroughly. Compared with other methods, the proposed method requires neither a specific system setup nor an additional etch process, which is a tremendous cost-saving in mass production.

Paper Details

Date Published: 24 March 2017
PDF: 12 pages
Proc. SPIE 10147, Optical Microlithography XXX, 101471E (24 March 2017); doi: 10.1117/12.2257776
Show Author Affiliations
Lisong Dong, Institute of Microelectronics (China)
Wenhui Chen, Institute of Microelectronics (China)
Xiaojing Su, Institute of Microelectronics (China)
Yayi Wei, Institute of Microelectronics (China)
Univ. of Chinese Academy of Sciences (China)


Published in SPIE Proceedings Vol. 10147:
Optical Microlithography XXX
Andreas Erdmann; Jongwook Kye, Editor(s)

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