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Asymmetry overlay correction for lithography processes
Author(s): Ming-Jui Chen; Chun-Chi Yu; Tang Chun Weng; C.-H. Chang; Charlie Chen; Chia Ching Lin; En Chuan Lio; Chia Hsiang Yu
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Paper Abstract

Overlay control for semiconductor devices is getting tighter in recent years. In the past, we may only concern the whether the overlay are in spec or not. However, the spec we concerned was the same for both X and Y directions. To achieve the tighter spec in the future, we may consider the asymmetry specs for X and Y directions separately for some specific layers, such as CONT layer. For example, if the spec of X direction is tighter than Y direction, we can lose the precision of overlay from Y direction to let overlay from X direction more precise. Theoretically, the common overlay models such as HOPC or iHOPC set X and Y directions independently. To reach the goal of loss overly from one direction to preserve the overlay from the other direction, we consider the full map measurement overlay historical data. From these data, we can analyze the data to find which overlay targets are more important to X direction, and we can set these corresponding targets as the new measurement locations. This is one concept of “asymmetry” since the chosen measurement locations can provide more precisely correction for the overlay of specific direction. On the other hand, we use the in spec ratio (ISR) index for all measurement overlay targets on wafer to replace the traditional mean plus 3 sigma (M3S) index, since we have the budgets of both X and Y directions. The in spec ratio is defined as ratio that the residuals of X and Y directions fill the corresponding budgets, simultaneously. Since our goal is to maximize the ISR, the traditional M3S optimization algorithm can be replaced by ISR optimization with different overlay specs. That is the reason we call “asymmetry overlay correction”.

Paper Details

Date Published: 28 March 2017
PDF: 8 pages
Proc. SPIE 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 1014525 (28 March 2017); doi: 10.1117/12.2257631
Show Author Affiliations
Ming-Jui Chen, United Microelectronics Corp. (Taiwan)
Chun-Chi Yu, United Microelectronics Corp. (Taiwan)
Tang Chun Weng, United Microelectronics Corp. (Taiwan)
C.-H. Chang, United Microelectronics Corp. (Taiwan)
Charlie Chen, United Microelectronics Corp. (Taiwan)
Chia Ching Lin, United Microelectronics Corp. (Taiwan)
En Chuan Lio, United Microelectronics Corp. (Taiwan)
Chia Hsiang Yu, Kernel System Corp. (Taiwan)


Published in SPIE Proceedings Vol. 10145:
Metrology, Inspection, and Process Control for Microlithography XXXI
Martha I. Sanchez, Editor(s)

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