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Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices
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Paper Abstract

Directed Self Assembly (DSA) has emerged as one of the most compelling next generation patterning techniques for sub-7nm via or contact layers. A key issue in enabling DSA as a mainstream patterning technique is the generation of grapho-epitaxy based guiding pattern (GP) shapes to assemble the contact patterns on target with high fidelity and resolution. Current GP generation is mostly empirical, and limited to a very small number of via configurations. In this paper, we propose the first model-based GP synthesis algorithm and methodology for on-target and robust DSA, on general via pattern configurations. The final post-RET printed GPs derived from our original synthesized GPs are resilient to process variations and continue to maintain the same DSA fidelity in terms of placement error and target shape.

Paper Details

Date Published: 21 March 2017
PDF: 12 pages
Proc. SPIE 10144, Emerging Patterning Technologies, 101440G (21 March 2017); doi: 10.1117/12.2257313
Show Author Affiliations
Joydeep Mitra, Mentor Graphics Corp. (United States)
Andres Torres, Mentor Graphics Corp. (United States)
David Z. Pan, The Univ. of Texas at Austin (United States)

Published in SPIE Proceedings Vol. 10144:
Emerging Patterning Technologies
Christopher Bencher, Editor(s)

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