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Proceedings Paper

The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7
Author(s): Raf Appeltans; Pieter Weckx; Praveen Raghavan; Ryoung-Han Kim; Gouri Sankar Kar; Arnaud Furnémont; Liesbet Van der Perre; Wim Dehaene
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Paper Abstract

Static Random Access Memory (SRAM) cells are used together with logic standard cells as the benchmark to develop the process flow for new logic technologies. In order to achieve successful integration of Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as area efficient higher level embedded cache, it also needs to be included as a benchmark. The simple cell structure of STT-MRAM brings extra patterning challenges to achieve high density. The two memory types are compared in terms of minimum area and critical design rules in both the iN10 and iN7 node, with an extra focus on patterning options in iN7. Both the use of Self-Aligned Quadruple Patterning (SAQP) mandrel and spacer engineering, as well as multi-level via’s are explored. These patterning options result in large area gains for the STT-MRAM cell and moreover determine which cell variant is the smallest.

Paper Details

Date Published: 28 March 2017
PDF: 13 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480G (28 March 2017); doi: 10.1117/12.2255089
Show Author Affiliations
Raf Appeltans, KU Leuven (Belgium)
IMEC (Belgium)
Pieter Weckx, IMEC (Belgium)
Praveen Raghavan, IMEC (Belgium)
Ryoung-Han Kim, IMEC (Belgium)
Gouri Sankar Kar, IMEC (Belgium)
Arnaud Furnémont, IMEC (Belgium)
Liesbet Van der Perre, KU Leuven (Belgium)
Wim Dehaene, KU Leuven (Belgium)
IMEC (Belgium)


Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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