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Proceedings Paper

Improvement of sidewall roughness of sub-micron silicon-on-insulator waveguides for low-loss on-chip links
Author(s): Cyril Bellegarde; Erwine Pargon; Corrado Sciancalepore; Camille Petit-Etienne; Vincent Hughes; Jean-Michel Hartmann; Philippe Lyan
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Paper Abstract

We report the successful fabrication of low-loss sub-micrometric Silicon-On-Insulator strip waveguides for on-chips links. Several strategies including post-lithography treatment, and post-Silicon smoothening techniques such as thermal oxidation and hydrogen annealing have been investigated to smoothen the waveguide sidewalls, as roughness is the major source of transmission losses. An extremely low silicon line edge roughness of 0.75nm is obtained with the optimized process flow combining resist mask Si patterning and hydrogen annealing at 850°C. As a result, record low optical losses of less than 0.5dB/cm are measured at 1310nm for waveguide dimensions superior to 500nm. They range from 2dB/cm to 0.8dB/cm for 300-400nm wide waveguides. Those results are to our knowledge the best ever published for a 1310nm wavelength.

Paper Details

Date Published: 23 February 2017
PDF: 14 pages
Proc. SPIE 10108, Silicon Photonics XII, 1010816 (23 February 2017); doi: 10.1117/12.2250344
Show Author Affiliations
Cyril Bellegarde, Univ. Grenoble Alpes (France)
Lab. des Technologies de La Microélectronique, CNRS (France)
CEA-LETI, MINATEC (France)
Erwine Pargon, Univ. Grenoble Alpes (France)
Lab. des Technologies de La Microélectronique, CNRS (France)
CEA-LETI, MINATEC (France)
Corrado Sciancalepore, CEA-LETI, MINATEC (France)
Camille Petit-Etienne, Univ. Grenoble Alpes (France)
Lab. des Technologies de La Microélectronique, CNRS (France)
CEA-LETI, MINATEC (France)
Vincent Hughes, CEA-LETI, MINATEC (France)
Jean-Michel Hartmann, CEA-LETI, MINATEC (France)
Philippe Lyan, CEA-LETI, MINATEC (France)


Published in SPIE Proceedings Vol. 10108:
Silicon Photonics XII
Graham T. Reed; Andrew P. Knights, Editor(s)

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