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Proceedings Paper

An FPGA-based reconfigurable DDC algorithm
Author(s): B. Juszczyk; G. Kasprowicz
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Paper Abstract

This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

Paper Details

Date Published: 28 September 2016
PDF: 6 pages
Proc. SPIE 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, 100314Y (28 September 2016); doi: 10.1117/12.2249318
Show Author Affiliations
B. Juszczyk, Warsaw Univ. of Technology (Poland)
G. Kasprowicz, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 10031:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016
Ryszard S. Romaniuk, Editor(s)

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